1. Field of the Invention
The present invention relates to a memory operating system for encoding and decoding data, and particularly, to a segment-based pixel processing apparatus and a method for effective memory operation.
2. Description of the Related Art
In general, pre-processing or post-processing is performed on an encoded or decoded image signal in order to improve the quality of an image. Here, the pre-processing or post-processing is performed in pixel units.
Referring to FIG. 1, input pixel data is temporarily stored in a frame memory (not shown) in frames units or field units. The pixel data stored in frame or field units is read by a memory for processing. As illustrated in FIG. 1, in general, the pixel data is pre-processed or post-processed through several line memories, starting from the uppermost line of the frame to its lowermost line from left to right. That is, pixel data within a frame is sequentially pre-processed or post-processed in the sequence of row #0→row #1→row #2→row #3→row #4, . . . , etc.
Referring to FIG. 2, let us assume that the neighbor pixels at n−1th and n+1th rows necessary for pre-processing or post-processing a pixel at an nth row are present right above and under the pixel at the nth row. The pixels at the n−1th, nth, and n+1th rows are input to a processor 240 via a first line memory 210, a second line memory 220, and a third line memory 230, respectively.
For instance, assuming that an image signal having 720 pixels×480 lines is present within a frame, a conventional hardware structure for performing low-pass filtering on 3 pixels×3 pixels requires three line memories capable of storing at least 720 pixels. That is, the conventional hardware structure requires line memory of about 2.2 Kbytes.
Accordingly, as more frames are required to be processed and the number of pixels above and under each target pixel increases, a conventional pixel processing method requires more line memory to perform pre-processing or post-processing on the increased number of pixels.